General Guidelines

-No glue logic at the top

-Guidelines for FSM synthesis

The following guidelines are presented for writing finite state machines that may help in optimizing the logic:

a) State names should be described using "enumerated types" in VHDL, or "parameters" in Verilog.
b) Combinational logic for computing the next state should be in its own process or always, separate from the state registers.
c) Implement the next-state combinational logic with a case statement.

-Latches

are simple devices, therefore they cover less area as compared to their counterparts, flip-flops. However, latches in general are more troublesome because their presence in a design makes DFT scan insertion difficult, although not impossible. It is also complicated to perform static timing analysis on designs containing latches, due to thier ability of being transparent when enabled. For this reason, designers generally prefer filp-flops to latchs.

-Three-State Interface

Tri-state logic is inferred when high impedance (Z) is assigned to an output. Arbitrary use of tri-state logic is generally not recommended because of the following reasons:

a) Tri-state logic reduces testability.
b) Tri-state logic is difficult to optimize - since it cannot be buffered. This can lead to max_fanout violations and heavily loaded nets.

On the upside however, tri-state logic can provide significant savings in area.

from Himanshu Bhatnagar, "Advanced ASIC chip synthesis," 2002